1. Field of the Invention
The present invention relates to a semiconductor memory device and a method of driving the same, and more particularly, to a semiconductor memory device with hierarchical column selection lines, and a method of driving the same.
2. Description of the Related Art
A semiconductor memory device, and in particular, a synchronous dynamic random access memory (SDRAM) performing high-frequency operations, performs various commands in synchronization with a reference clock signal. Read/write characteristics are significant factors that determine the performance of the SDRAM. For instance, in the case of an SDRAM operating in response to a high frequency clock signal, e.g. 100 Mhz, the margin for enabling and disabling column line signals is significantly reduced.
FIG. 1 is a block diagram illustrating a part of a conventional semiconductor memory device. Referring to FIG. 1, the conventional semiconductor memory device includes memory cell arrays. The individual memory cells are comprised of a plurality of rows and columns arranged in the form of a matrix. A semiconductor memory device may be composed of at least one memory cell array as illustrated in FIG. 1. FIG. 1 illustrates a first memory cell array 11 and an nth memory cell array 12. Word line driving units 21 and 22, that drive word lines of memory cell arrays, are respectively connected to the first and nth memory cell arrays 11 and 12.
Each of the first and nth memory cell arrays 11 and 12 is connected to sense amplifiers that amplify the difference in voltage between a bit line (BL) and a complementary bit line (/BL) pair to perform a read operation. Referring to FIG. 1, sense amplifiers 31 and 32 are respectively connected to a BL and pair of the first memory cell array 11, and sense amplifiers 33 and 34 are respectively connected to a BL and pair of the nth memory cell array 12.
The conventional semiconductor memory device of FIG. 1 includes column selection line driving units 41 and 42 that respectively generate column selection signals transmitted via column selection lines CSL0 and CSL1. The conventional semiconductor memory device further includes, pairs of column selection gates 51 through 54. Each column selection gate pair is switched on or off to electrically connect or disconnect the corresponding BL and pair to a pair of input/output (I/O) lines IO and /IO, in response to the column selection signals. US Patent Publication No. US2004-202029 discloses column selection lines of a semiconductor memory device and a method of driving the same. The IO and /IO lines are respectively connected to data I/O circuits 61 and 62.
Each of the column selection gate pairs 51 through 54 is comprised of switching devices. FIG. 1 illustrates two NMOS transistors, N1 and N2 as an exemplary embodiment of the switching devices. N1 is connected between the IO line and the BL. N2 is connected between the /IO line and the . A column selection signal is generated by the column selection line driving unit 41 to enable or disable the column selection gate pair 51. The signal is transmitted to the gate electrodes of the NMOS transistors N1 and N2 via the column selection line CSL0, thereby controlling the switching on and off of the NMOS transistors N1 and N2.
The column selection lines CSL0 and CSLn are often metal lines having a large capacitance. The column line signals transmitted via the column selection lines CSL0 and CSLn must toggle twice, from a logic low level to a logic high level and vice versa, during a cycle of a predetermined reference clock signal. When the column selection signal is toggled to the logic high level, the column selection gate pair 51 is turned on to electrically connect the BL, /BL, IO line, and /IO line to receive or output data. Next, when the column selection signal is toggled to the logic low level to turn off the BL, /BL, IO line, and /IO line, a predetermined precharge circuit (not shown) pre-charges the BL and /BL to a predetermined level.
As semiconductor memory devices have been developed to operate at high speeds, the speed of toggling the column selection signal must be improved so that the column selection signal can be toggled twice during a cycle of a predetermined high-frequency reference clock signal. However, a load on the column selection lines CSL0 and CSLn is increased due to the capacitance of the column selection lines CSL0 and CSLn via which the column selection signals are transmitted.
In addition, the higher the capacity of a semiconductor memory device, the greater the size and number of the memory cell arrays. As illustrated in FIG. 1, the load on the column selection lines CSL0 and CSLn via which the column selection signal is transmitted to each memory cell array, is also increased. Accordingly, there is a limitation to increasing the speed of toggling the column selection signal, thereby causing problems which will be described below with reference to FIG. 2.
FIG. 2 is a waveform diagram illustrating the state of a column selection signal toggled according to the frequency of an operating clock signal. FIG. 2 illustrates the waveforms of a high-frequency operating clock signal CLKa and a low-frequency operating clock signal CLKb, and column selection signals transmitted via column selection lines.
When data is input or output in response to the high-frequency operating clock signal CLKa having a cycle of Ta, a column selection signal CLSa transmitted via a column selection line has a waveform shape indicated by a dotted line. However, the column selection signal CLSa transmitted via a column selection line is not toggled enough to reach a logic high level or a logic low level during half the cycle of Ta, since the toggling speed of the column selection signal is low. Thus, data output from a pair of bit lines is not completely transmitted to a pair of I/O lines, thereby degrading the high-speed performance of a semiconductor memory device.
In contrast, when data is input or output in response to the low-frequency operating clock signal CLKb having a cycle of Tb, the column selection signal is sufficiently toggled to a logic high level or a logic low level for half the cycle of Tb even when the column selection signal CLSb is transmitted via a column selection line on which a load is applied, thereby enabling the semiconductor memory device to stably operate.
A column selection signal transmitted via a column selection line must toggle twice during an operating clock signal cycle. Due to this fact, the frequency characteristics of the column selection line have a greater influence on the column selection signal than data signals transmitted across a pair of I/O lines. Reducing the load on the column selection line improves the frequency characteristics. However, the load on the column selection line is determined by the metal line of the column selection line CSL, the structures within the column selection gate pairs, and process conditions. Once the structure within the column selection gate pairs and the process conditions are determined, the load on the column selection line is fixed, thereby making the semiconductor memory device difficult to operate at high speeds.